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Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic.

• Authors : Reddy, M. Devendra¹ ; Dass, P.²

• Source: Alinteri Journal of Agriculture Sciences. 2021, Vol. 36 Issue 1, p635-641. 7p.

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Wanhammar L.: A Robust Differential Logic Style with NMOS Logic Nets

• Authors : Magnus Karlsson; Mark Vesterbacka; Lars Wanhammar ...

• Source: http://www.es.isy.liu.se/publications/papers_and_reports/1997/DNlogicIWSSIP97.pdf.

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Design and Implementation of the Combinational Circuits Using Low Power Adiabatic Logic Techniques

• Authors : Dr. A. Gangadhar

Subjects: Adiabatic; Pass Transistor Logic; Combinational Circuits

• Source: Engineering and Technology Journal, 07(02), 1169-1174, (2022-02-12)

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Low power combinational circuit based on Pseudo NMOS logic

• Authors : Rajeev Kumar; Vimal Kant Pandey; The Pennsylvania State University CiteSeerX Archives

• Source: http://www.erpublications.com/uploaded_files/download/download_10_04_2014_17_03_46.pdf.

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2-Bit CMOS Comparator by Hybridizing PTL and Pseudo Logic

• Authors : Ana Choudhary; Rajesh Mehra; The Pennsylvania State University CiteSeerX Archives

Subjects: Magnitude comparator; Binary Comparator; High speed

• Source: http://www.ijrte.org/attachments/File/v2i2/B0564052213.pdf.

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Bulk Carrier Contaminations and Their Effects on MOSFETs Under Energy Harvesting Systems

• Authors : Yuta Watanabe; Takaya Sugiura; Nobuhiko Nakano

Subjects: Analog LSI; energy harvesting; Internet of Things

• Source: IEEE Journal of the Electron Devices Society, Vol 12, Pp 450-456 (2024)

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Ultra-low power DLMS adaptive filter for hearing aid applications

• Authors : Hyung-il Kim; The Pennsylvania State University CiteSeerX Archives

Subjects: architecture; Sub-Pseudo NMOS; Sub-CMOS

• Source: http://www.ece.umn.edu/groups/VLSIresearch/papers/conferences/ISLPED01.pdf.

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Efficient adders for assistive devices

• Authors : Mansi Jhamb; Gitanjali

Subjects: BANs-Body Area Networks; Body sensor networks; CSC-completion sensing circuit

• Source: Engineering Science and Technology, an International Journal, Vol 20, Iss 1, Pp 95-104 (2017)

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DESIGN OF LOW LEAKAGE CURRENT AVERAGE POWER CMOS CURRENT COMPARATOR USING SVL TECHNIQUE WITH PSEUDO NMOS AND TRANSMISSION GATE LOGICS

• Authors : Dinesh Kumar, T.R.; Sundaram, K.Mohana; Bennet, M.Anto

Subjects: current comparator; SVL circuit; pseudo nmos

• Source: International Journal on Smart Sensing and Intelligent Systems, 10(4), (2017-09-01)

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K.Roy(2003) : “Ultra-Low Power DLMS Adaptive Filter for Hearing Aid Applications” ,IEEE transactions on very large scale integration (VLS1) system

• Authors : Hyung-il Kim; Kaushik Roy; The Pennsylvania State University CiteSeerX Archives

Subjects: architecture; Sub-Pseudo NMOS; Sub-CMOS

• Source: http://www.cecs.uci.edu/~papers/compendium94-03/papers/2001/islped01/pdffiles/p352.pdf.

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