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Power-Optimized Digitally Controlled Oscillator in 28-nm CMOS for Low-Power FMCW Radars

• Authors : Chicco, Francesco; Rengifo, Sammy Cerida; Pengg, Franz X.

• Source: IEEE Microwave and Wireless Components Letters ; volume 31, issue 8, page 965-968 ; ISSN 1531-1309 1558-1764

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A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator

• Authors : Liu, Jen-Chieh; Li, Yu-Ping

• Source: IEEE Access ; volume 9, page 39717-39726 ; ISSN 2169-3536

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Demonstration videos of Erkki Kurenniemi's DICO - a digitally controlled oscillator for composer Osmo Lindeman

• Authors : Ojanen, Mikko

Subjects: Kurenniemi Erkki; Lindeman Osmo; DICO - digitally controlled oscillator

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A Ka-Band Dual-Band Digitally Controlled Oscillator With −195.1-dBc/Hz FoM${_T}$ Based on a Compact High-$Q$ Dual-Path Phase-Switched Inductor

• Authors : Baylon, Joe; Agarwal, Pawan; Renaud, Luke ...

• Source: IEEE Transactions on Microwave Theory and Techniques ; volume 67, issue 7, page 2748-2758 ; ISSN 0018-9480 1557-9670

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A Low-jitter Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Optimally Spaced TDC for Flicker-Noise Reduction

• Authors : Hwang, Chanwoong; Park, Hangi; Lee, Yongsun ...

Subjects: Ring digitally-controlled oscillator (RDCO); digital phase-locked-loop (DPLL); time-to-digital converter (TDC)

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Design of a Linear LC Digitally Controlled Oscillator Using Topographical Field Maps

• Authors : Abdullah, Shakeeb

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A 0.016 mm2 0.26- μ W/MHz 60–240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS ; A 0.016 mm 2 0.26-μW/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

• Authors : Zhu, Junheng; Choi, Woo Seok; Hanumolu, Pavan Kumar ...

Subjects: PHASE-LOCKED LOOPNOISE; Phase-locked loops (PLLs)RC relaxation oscillator (RCO)digital PLL (DPLL)integer-Nperiod jitterdigitally controlled ring oscillator (DCRO)

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8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS

• Authors : Shu, Guanghua; Choi, Woo-Seok; Saxena, Saurabh ...

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The Bang Bang PLL as a Clock Source in Serial-De-Serializer (SERDES) Applications

• Authors : Smith, Raleigh Robert

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Time-domain modelling and performance research of millimeter-wave all-digital phase-locked loop

• Authors : Xu, Shuning; Tang, Lu; Yang, Junhao

• Source: Journal of Physics: Conference Series ; volume 2245, issue 1, page 012018 ; ISSN 1742-6588 1742-6596

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