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  • 1-10 of  12 نتائج ل ""Plesco, Alexandru""

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Collection : Hal Lyon 1 (University Claude Bernard Lyon 1) فلترة بواسطة : مؤلف
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Conference

Data-Aware Process Networks

Subjects: High-Level Synthesis; Polyhedral Model; FPGAVirtual; South Korea

  • Source: CC 2021 - 30th ACM SIGPLAN International Conference on Compiler Construction ; https://inria.hal.science/hal-03143777 ; CC 2021 - 30th ACM SIGPLAN International Conference on Compiler Construction,

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Academic Journal

Optimizing Affine Control with Semantic Factorizations ; Optimisation du contrôle affine avec des factorisations sémantiques

Subjects: Polyhedral Analysis and Optimizations; Affine Control; High-level synthesis

  • Source: ISSN: 1544-3566.

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Conference

Automatic Generation of FPGA-Specific Pipelined Accelerators

Subjects: High-level synthesis; Polyhedral Model; Pipelined floating-point operatorsBelfast; United Kingdom

  • Source: LNCS 6578, Springer ; International Symposium on Applied Reconfigurable Computing (ARC'11) ; https://hal-ens-lyon.archives-ouvertes.fr/ensl-00549682 ; International Symposium on Applied Reconfigurable

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Conference

An FPGA architecture for solving the Table Maker's Dilemma

Subjects: table maker's dilemma; floating-point arithmetic; correct roundingSanta Monica; United States

  • Source: Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors ; Application-Specific Systems, Architectures and Processors (ASAP), 2011 IEEE

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Conference

Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators ; Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators : An Experience With the Altera C2H HLS Tool

Subjects: optimized communications; FPGA; High-level synthesis toolsRennes; France

  • Source: IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'10) ; https://inria.hal.science/hal-01664033 ; IEEE International Conference on Application-specific

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Report

High-Level Synthesis of Pipelined FSM from Loop Nests

Subjects: High-level synthesis; fine-grain loop optimization; control automaton

  • Source: https://inria.hal.science/hal-01301334 ; [Research Report] 8900, INRIA. 2016, pp.18.

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Report

Data-aware Process Networks

Subjects: automatic parallelization; High-level Synthesis; polyhedral compilation

  • Source: https://inria.hal.science/hal-01158726 ; [Rapport de recherche] RR-8735, Inria - Research Centre Grenoble – Rhône-Alpes; INRIA. 2015, pp.32.

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Report

Program Analysis and Source-Level Communication Optimizations for High-Level Synthesis

Subjects: [INFO.INFO-DC]Computer Science [cs]/Distributed; Parallel; and Cluster Computing [cs.DC]

  • Source: https://inria.hal.science/inria-00601822 ; [Research Report] RR-7648, INRIA. 2011, pp.16.

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Report

FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores

Subjects: High-Level Synthesis; Compiler; ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic

  • Source: https://inria.hal.science/inria-00606977 ; [Research Report] RR-7674, INRIA. 2011, pp.33.

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Report

Kernel Offloading with Optimized Remote Accesses

Subjects: Polyhedral optimizations; communication optimizations; pipelined processes

  • Source: https://inria.hal.science/inria-00611179 ; [Research Report] RR-7697, INRIA. 2011, pp.29.

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  • 1-10 of  12 نتائج ل ""Plesco, Alexandru""