- Patent Number:
12068,402
- Appl. No:
17/538135
- Application Filed:
November 30, 2021
- نبذة مختصرة :
The present disclosure generally relates to dopant profile control in a heterojunction bipolar transistor (HBT). In an example, a semiconductor device structure includes a semiconductor substrate and an HBT. The HBT includes a collector region, a base region, and an emitter region. The base region is disposed on or over the collector region. The emitter region is disposed on or over the base region. The base region is disposed on or over the semiconductor substrate and includes a heteroepitaxial sub-layer. The heteroepitaxial sub-layer is doped with a dopant. A concentration gradient of the dopant increases from a region in a layer adjoining and overlying the heteroepitaxial sub-layer to a peak concentration in the heteroepitaxial sub-layer without decreasing between the region and the peak concentration.
- Inventors:
TEXAS INSTRUMENTS INCORPORATED (Dallas, TX, US)
- Assignees:
Texas Instruments Incorporated (Dallas, TX, US)
- Claim:
1. A method of forming an integrated circuit, the method comprising: epitaxially growing a first sub-layer of a base region on or over a collector region, the first sub-layer having a first uniform concentration of a semiconductor species, the collector region being disposed on or over a semiconductor substrate; epitaxially growing a second sub-layer of the base region on or over the first sub-layer, the second sub-layer having a second uniform concentration of the semiconductor species, said epitaxially growing the second sub-layer comprising doping the second sub-layer with a first dopant; and epitaxially growing a third sub-layer of the base region on or over the second sub-layer, the third sub-layer having a third uniform concentration of the semiconductor species, the second concentration less than the first concentration and less than the third concentration.
- Claim:
2. The method of claim 1 , wherein epitaxially growing each sub-layer of the first sub-layer and the third sub-layer comprises doping the respective sub-layer with a second dopant different from the first dopant.
- Claim:
3. The method of claim 2 , wherein the second dopant is carbon.
- Claim:
4. The method of claim 1 , wherein the first dopant is an n-type dopant.
- Claim:
5. The method of claim 4 , wherein the n-type dopant is phosphorus, arsenic, or a combination thereof.
- Claim:
6. The method of claim 1 , wherein epitaxially growing each sub-layer of the first sub-layer and the third sub-layer does not include doping the respective sub-layer with the first dopant.
- Claim:
7. The method of claim 1 , wherein the semiconductor species is germanium.
- Claim:
8. The method of claim 1 , wherein epitaxially growing each sub-layer of the second sub-layer and the third sub-layer is performed at a respective temperature less than or equal to 650° C.
- Claim:
9. The method of claim 8 , wherein epitaxially growing each sub- layer of the second sub-layer and the third sub-layer is performed at a respective temperature of about 570° C.
- Claim:
10. The method of claim 1 further comprising: epitaxially growing a fourth sub-layer of the base region on or over the collector region, the first sub-layer being epitaxially grown on or over the fourth sub-layer; epitaxially growing a fifth sub-layer of the base region on or over the third sub-layer, wherein each sub-layer of the fourth sub-layer and the fifth sub-layer is epitaxially grown with the semiconductor species, a concentration of the semiconductor species in the fourth sub-layer being less than the concentration of the semiconductor species in the first sub-layer, a concentration of the semiconductor species in the fifth sub-layer being less than the concentration of the semiconductor species in the third sub-layer; epitaxially growing a cap sub-layer of the base region on or over the fifth sub-layer; and epitaxially growing an emitter region on or over the cap sub-layer.
- Claim:
11. A method of forming a transistor of an integrated circuit, the method comprising: forming a collector region on or over a semiconductor substrate, a material of the collector region being silicon; forming a base region on or over the collector region, forming the base region comprising: forming a first base sub-layer on or over the collector region, a material of the first base sub-layer being silicon germanium; forming a second base sub-layer on or over the first base sub-layer, a material of the second base sub-layer being silicon germanium, a concentration of germanium in the second base sub-layer being greater than a concentration of germanium in the first base sub-layer; forming a third base sub-layer on or over the second base sub-layer, a material of the third base sub-layer being silicon germanium, a concentration of germanium in the third base sub-layer being less than the concentration of germanium in the second base sub-layer, epitaxially growing the third base sub-layer includes doping the third base sub-layer with phosphorus; forming a fourth base sub-layer on or over the third base sub-layer, a material of the fourth base sub-layer being silicon germanium, a concentration of germanium in the fourth base sub-layer being greater than the concentration of germanium in the third base sub-layer; forming a fifth base sub-layer on or over the fourth base sub-layer, a material of the fifth base sub-layer being silicon germanium, a concentration of germanium in the fifth base sub-layer being less than the concentration of germanium in the fourth base sub-layer; and forming a cap sub-layer on or over the fifth base sub-layer, a material of the cap sub-layer being silicon; and forming an emitter region on or over the base region.
- Claim:
12. The method of claim 11 , wherein forming each sub-layer of the second base sub-layer and the fourth base sub-layer includes doping the respective sub-layer with carbon.
- Claim:
13. The method of claim 11 , wherein forming each sub-layer of the third base sub-layer and the fourth base sub-layer is performed at a respective temperature less than or equal to 650° C.
- Claim:
14. The method of claim 11 , wherein forming each sub-layer of the third base sub-layer and the fourth base sub-layer is a respective selective epitaxial growth that includes using an etchant gas.
- Claim:
15. A method of forming an integrated circuit including a heterojunction bipolar transistor (HBT), the method comprising: forming a base region of the HBT, the base region located on or over a collector region of the HBT and including silicon and germanium, the HBT located over a semiconductor substrate having a top surface, the base region having a germanium concentration along a direction orthogonal to the top surface that has first and second local maxima of the germanium concentration, and a local minimum of the germanium concentration between the first and second local maxima.
- Claim:
16. A method of forming an integrated circuit, the method comprising: epitaxially growing a first sub-layer of a base region on or over a collector region if a heterojunction bipolar transistor, the collector region being disposed on or over a semiconductor substrate and having a first germanium concentration; epitaxially growing a second sub-layer of the base region on or over the first sub-layer, the second sub-layer having a second germanium concentration less than the first germanium concentration; and epitaxially growing a third sub-layer of the base region on or over the second sub-layer, the third sub-layer having a third germanium concentration greater than the second germanium concentration.
- Claim:
17. A method of forming an integrated circuit, comprising: forming a first semiconductor region having a first conductivity type extending into a semiconductor substrate having a top surface; forming a compound semiconductor region having an opposite second conductivity type over the first semiconductor region, the compound semiconductor region having first and second semiconductor species, a concentration of the second semiconductor species along a direction orthogonal to the top surface having first and second local maxima and a local minimum between the first and second local maxima, wherein the first semiconductor species is silicon and the second semiconductor species is germanium; and forming a second semiconductor region having the first conductivity type over the compound semiconductor region.
- Claim:
18. The method as recited in claim 17 , wherein the first semiconductor region is a collector of a heterojunction bipolar transistor (HBT), the compound semiconductor region is a base of the HBT and the second semiconductor region is an emitter of the HBT.
- Claim:
19. The method as recited in claim 17 , wherein the compound semiconductor region includes a first sublayer between the first local maximum and the first semiconductor region, and a second sublayer between the second local maximum and the second semiconductor region, the first and second sublayers having a concentration of the second semiconductor species greater than the local minimum concentration.
- Patent References Cited:
- Other References:
Lin; Base Doping Profile Control for SiGe PNP HBTs; Ph.D. Dissertation, The University of British Columbia, 2016. (Year: 2016). cited by examiner
- Primary Examiner:
Gheyas, Syed I
- Attorney, Agent or Firm:
Ralston, Andrew R.
Cimino, Frank D.
- الرقم المعرف:
edspgr.12068402
Processing Request
No Comments.