Static RAM for differential power analysis resistance

9,886,999

15/437452

February 21, 2017

The present invention discloses a static RAM for defensive differential power consumption analysis, comprising a replica bit-line circuit, a decoder, an address latch circuit, a clock circuit, n-bit memory arrays, n-bit data selectors, n-bit input circuit and n-bit output circuits; the output circuits comprises a sensitivity amplifier and a data latch circuit; the 1st PMOS tube, the 2nd PMOS tube, the 3rd PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 1st NMOS tube, the 2nd NMOS tube, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube constitute the sensitivity amplifier; two NOR gates, the 8th PMOS tube, the 9th PMOS tube, the 10th PMOS tube, the 11th PMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube and the 10th NMOS tube constitute the data latch circuit; the present invention is characterized in that energy consumption in each working cycle is basically identical, which is provided with higher capability in defense of differential power analysis.

Ningbo University (Zhejiang, CN)

Ningbo University (Zhejiang, CN)

1. A static RAM for Differential Power Analysis Resistance, comprising: a replica bit-line circuit; a decoder; an address data latch circuit; a clock circuit; n-bit memory arrays; n-bit data selectors; n-bit input circuits; and n-bit output circuits, wherein n-bit is an integral equal to or over 1, wherein the said decoder is connected to the said replica bit-line circuit, the said address data latch circuit, the said n-bit memory arrays and the said n-bit data selectors respectively, and the said clock circuit is connected to the said replica bit-line circuit, the said n-bit input circuits, the said n-bit output circuits respectively, wherein the jth input circuit is connected to the jth data selector; the said replica bit-line circuit is connected to the said n-bit output circuits, the said jth data selector is connected to the said jth memory array and the said jth output circuit respectively, j=1, 2, . . . , n, wherein the said output circuit comprises a sensitivity amplifier and a data latch circuit, which is characterized in that the said sensitivity amplifier comprises a 1st, a 2nd, a 3rd, a 4th, a 5th, a 6th and a 7th PMOS transistors and a 1st, a 2nd, the 3rd, a 4th and a 5th NMOS transistors, wherein a source of the 1st PMOS transistor, a source of the 4th PMOS transistor and a source of the 5th PMOS transistor are connected to a power supply respectively; a drain of the 1st PMOS transistor and a source of the 2nd PMOS transistor are connected to a source of the 3rd PMOS transistor; a drain of the 2nd PMOS transistor, a gate of the 3rd PMOS transistor, a drain of the 4th PMOS transistor, a drain of the 6th PMOS transistor, a drain of the 1st NMOS transistor and a gate of the 2nd NMOS transistor are connected to a drain of the 4th NMOS transistor respectively, and a common connection thereof is a 1st output terminal of the said sensitivity amplifier, wherein a gate of the 2nd PMOS transistor, a drain of the 3rd PMOS transistor, a drain of the 5th PMOS transistor, a drain of the 7th PMOS transistor, a gate of the 1st NMOS transistor and a drain of the 2nd NMOS transistor are connected to a drain of the 5th NMOS transistor respectively, and a common connection thereof is a 2nd input terminal of the said sensitivity amplifier, wherein a gate of the 1st PMOS transistor and a gate of the 4th NMOS transistor are connected to a gate of the 5th NMOS transistor, and a common connection thereof is a SADIS terminal of the said sensitivity amplifier, wherein the SADIS terminal of the said sensitivity amplifier is used to couple discharging signals to sensitivity amplifier, wherein a gate of the 4th PMOS transistor is connected to a gate of the 5th PMOS transistor, and a common connection thereof is a SAPRE terminal of the said sensitivity amplifier, the SAPRE terminal of the said sensitivity amplifier is used to couple charging signals to the sensitivity amplifier, wherein a gate of the 6th PMOS transistor is connected to a gate of the 7th PMOS transistor, and a common connection thereof is a SASEL terminal of the said sensitivity amplifier, the SASEL terminal of the said sensitivity amplifier is used to couple read signals to the sensitivity amplifier, wherein a gate of the 3rd NMOS transistor serves as a SAE terminal of the said sensitivity amplifier, the SAE terminal of the said sensitivity amplifier is used to couple enabling signals to the sensitivity amplifier, wherein a source of the 1st NMOS transistor and a source of the 2nd NMOS transistor are connected to the drain of the 3rd NMOS transistor respectively, and a source of the 3rd NMOS transistor, a source of the 4th NMOS transistor and a source of the 5th NMOS transistor are grounded respectively, wherein a source of the 6th PMOS transistor serves as a 1st signal input terminal of the said sensitivity amplifier, and a source of the 7th PMOS transistor serves as a 2nd signal input terminal of the said sensitivity amplifier, wherein the 1st signal input terminal of the said sensitivity amplifier serves as a BL terminal of the output circuit of the said static RAM, and the 2nd signal input terminal of the said sensitivity amplifier serves as a BLB terminal of the output circuit of the said static RAM, wherein the BL terminal and the BLB terminal of the output circuit of the said static RAM are used to connect the data selector to receive bit-line pairs, wherein the said data latch circuit comprises two NOR gates, a 8th PMOS, transistor, a 9th PMOS transistor, a 10th PMOS transistor, a 11th PMOS transistor, a 6th NMOS transistor, a 7th NMOS transistor, a 8th NMOS transistor, a 9th NMOS transistor and a 10th NMOS transistor, wherein the said two NOR gates comprise the 1st NOR gate and the 2nd NOR gate, and each of the said 1st and 2nd NOR gates comprises a 1st input terminal, a 2nd input terminal and an output terminal, wherein a source of the 9th PMOS transistor and a gate of the 6th NMOS transistor are connected to the power supply, the 1st input terminal of the 1st NOR gate serves as a 1st input terminal of the said data latch circuit, and the 1st input terminal of the said data latch circuit is connected to the 1st output terminal of the said sensitivity amplifier, wherein the 2nd input terminal of the 1st NOR gate, the output terminal of the 2nd NOR gate and a gate of the 10th PMOS transistor are connected to a gate of the 10th NMOS transistor, wherein the output terminal of the 1st NOR gate, the 1st input terminal of the 2nd NOR gate, a source of the 6th NMOS transistor, a source of the 11th PMOS transistor and a gate of the 8th PMOS transistor are connected to a gate of the 9th NMOS transistor, wherein the 2nd input terminal of the 2nd NOR gate serves as a 2nd input terminal of the said data latch circuit, and the 2nd input terminal of the said data latch circuit is connected to the 2nd input terminal of the said sensitivity amplifier, wherein a drain of the 9th PMOS transistor is connected to a source of the 8th PMOS transistor, wherein a gate of the 9th PMOS transistor is connected to a gate of the 7th NMOS transistor, and a common connection thereof is a OUTDIS terminal of the said data latch circuit, and the OUTDIS terminal of the said data latch circuit is used to receive discharging control signals from the output terminal, wherein a source of the 10th PMOS transistor, a drain of the 10th PMOS transistor, a drain of the 10th NMOS transistor, a source of the 10th NMOS transistor, a source of the 8th NMOS transistor, a source of the 9th NMOS transistor, a source of the 7th NMOS transistor and a gate of the 11th PMOS transistor are grounded, and a drain of the 6th NMOS transistor and a drain of the 11th PMOS transistor are connected to a gate of the 8th NMOS transistor, wherein a drain of the 8th PMOS transistor, a drain of the 8th NMOS transistor and a drain of the 9th NMOS transistor are connected to a drain of the 7th NMOS transistor, and common connection thereof is an output terminal of the said data latch circuit, and the output terminal of the said data latch circuit serves as an output terminal of the output circuit of the said static RAM.

2. The static RAM for Differential Power Analysis Resistance according to claim 1 , wherein the said input circuit comprises a 11th NMOS transistor, a 12th NMOS transistor, a 13th NMOS transistor, a 14th NMOS transistor, a 15th NMOS transistor, a 16th NMOS transistor, a 17th NMOS transistor, a 18th NMOS transistor, a 19 NMOS transistor, a 20th NMOS transistor, a 21st NMOS transistor, a 12th PMOS transistor, a 13th PMOS transistor, a 14th PMOS transistor, a 15th PMOS transistor, a 16th PMOS transistor, a 17th PMOS transistor, a 18th PMOS transistor, a 19th PMOS transistor, a 20th PMOS transistor, a 21st PMOS transistor, a 22nd PMOS transistor, a 23rd PMOS transistor and a 24th PMOS transistor, wherein a source of the 12th PMOS transistor, a source of the 14th PMOS transistor, a source of the 16th PMOS transistor, a source of the 17th PMOD transistor, a source of the 18th PMOS transistor, a source of the 20th PMOS transistor, a source of the 22nd PMOS transistor, a source of the 23rd PMOS transistor and a source of the 24th PMOS transistor are connected to the power supply respectively; a drain of the 12th PMOS transistor is connected to a source of the 13th PMOS transistor, wherein a drain of the 13th PMOS transistor, a drain of the 11th NMOS transistor, a drain of the 15th PMOS transistor and a drain of the 13th NMOS transistor, a gate of the 16th PMOS transistor are connected to a gate of the 15th NMOS transistor, wherein a source of the 11th NMOS transistor is connected to a drain of the 12th NMOS transistor, wherein a source of the 12th NMOS transistor, a source of the 14th NMOS transistor, a source of the 15th NMOS transistor, a source of the 19th NMOS transistor and a source of the 21st NMOS transistor are grounded respectively, wherein a drain of the 14th PMOS transistor is connected to a source of the 15th PMOS transistor, wherein a source of the 13th NMOS transistor is connected to a drain of the 14th NMOS transistor, wherein a gate of the 14th PMOS, a gate of the 14th NMOS transistor, a drain of the 15th NMOS transistor, a drain of the 16th PMOS transistor, a gate of the 17th PMOS transistor, a gate of 16th NMOS transistor, a gate of 19th NMOS transistor are connected to a gate of the 20th PMOS transistor, wherein a drain of the 17th PMOS transistor, a drain of the 16th NMOS transistor, a gate of the 17th NMOS transistor are connected to a gate of the 18th PMOS transistor, wherein a drain of the 17th NMOS transistor, a drain of the 18th PMOS transistor and a source of the 18th NMOS transistor are connected to the source of the 19th PMOS transistor, wherein a drain of the 18th NMOS transistor, a drain of the 19th PMOS transistor are connected to a drain of the 22nd PMOS transistor, and a common connection thereof is a 1st output terminal of the said input circuit, wherein a drain of the 19th NMOS transistor, a drain of the 20th PMOS transistor, a source of the 20th NMOS transistor are connected to a source of the 21st PMOS transistor, wherein a drain of the 20th NMOS transistor, a drain of the 21st PMOS transistor are connected to a drain of the 23rd PMOS transistor, and a common connection thereof is a 2nd output terminal of the said input circuit, wherein a gate of the 12th PMOS transistor, a gate of the 18th NMOS transistor, a gate of the 20th NMOS transistor, a gate of the 13th NMOS transistor and a gate of the 21st NMOS transistor are connected to a gate of the 24th PMOS transistor, and a common connection thereof is a clock signal input terminal of the said input circuit, used to receive write-in signals output from the said clock circuit, wherein a gate of the 12th NMOS transistor, a gate of the 15th PMOS transistor, a drain of the 24th PMOS transistor, a drain of the 21st NMOS transistor, a gate of the 19th PMOS transistor are connected to a gate of the 21st PMOS transistor, and a common connection thereof is an inverted clock signal input terminal of the said input circuit, used to receive inverted signals among write-in signals output from the said clock module, wherein a gate of the 13th PMOS transistor is connected to a gate of the 11th NMOS transistor, and a common connection thereof is a signal input terminal of the said input circuit, used to receive external data, wherein a gate of the 22nd PMOS transistor is connected to a gate of the 23rd PMOS transistor, and a common node is a charging signal input terminal of the said input circuit, used to receive charging signals output from the said clock circuit.

2006/0120142 June 2006 Yamagami

edspgr.09886999