- Document Number:
20240304708
- Appl. No:
18/326077
- Application Filed:
May 31, 2023
- نبذة مختصرة :
Disclosed are an insulated gate bipolar transistor and a method of manufacturing the same. More particularly, an insulated gate bipolar transistor and a method of manufacturing the same include a planar gate on a drift region or a first body region in a floating region of the insulated gate bipolar transistor, and if desired or necessary, a second trench gate in the first body region to increase an input capacitance (Cies) and prevent self-turn-on of the insulated gate bipolar transistor.
- Claim:
1. An insulated gate bipolar transistor comprising: a collector electrode; a collector on the collector electrode; a drift region on the collector; a plurality of first trench gates spaced apart from each other in the drift region; a first body region between first adjacent ones of the first trench gates and in the drift region; a second body region between second adjacent ones of the first trench gates and in the drift region; and a planar gate between the first adjacent ones of the first trench gates and on the first body region.
- Claim:
2. The insulated gate bipolar transistor of claim 1, further comprising: an interlayer insulating layer covering the planar gate, the first body region and the second body region; and an emitter electrode on the interlayer insulating layer, wherein the first body region floats.
- Claim:
3. The insulated gate bipolar transistor of claim 2, wherein a lowermost surface of the first body region is deeper in the drift region than a lowermost surface of the second body region.
- Claim:
4. The insulated gate bipolar transistor of claim 2, further comprising: an emitter in the second body region; and a body contact in the second body region, wherein the emitter is electrically connected to the emitter electrode.
- Claim:
5. The insulated gate bipolar transistor of claim 2, wherein the planar gate comprises: a gate insulating layer on the first body region; and a gate electrode on the gate insulating layer.
- Claim:
6. The insulated gate bipolar transistor of claim 2, further comprising a buffer layer on the collector.
- Claim:
7. An insulated gate bipolar transistor comprising: a collector electrode; a collector on the collector electrode; a drift region on the collector; a plurality of first trench gates spaced apart from each other in the drift region; a first body region between adjacent ones of the first trench gates and in the drift region; a second body region between different adjacent ones of the first trench gates and in the drift region; a planar gate between the different adjacent ones of the first trench gates and on the first body region; and a second trench gate in the first body region.
- Claim:
8. The insulated gate bipolar transistor of claim 7, wherein the second trench gate is connected to the planar gate.
- Claim:
9. The insulated gate bipolar transistor of claim 7, wherein the second trench gate has a lowermost surface in the first body region.
- Claim:
10. The insulated gate bipolar transistor of claim 7, wherein the second trench gate has a shallower depth than the first trench gates.
- Claim:
11. The insulated gate bipolar transistor of claim 10, wherein the second trench gate has a narrower width than the first trench gates.
- Claim:
12. The insulated gate bipolar transistor of claim 11, wherein the second trench gate comprises: a gate insulating layer on an inner wall of a trench; and a gate electrode on an inner wall of the gate insulating layer and filling the trench, wherein the first body region floats.
- Claim:
13. An insulated gate bipolar transistor comprising: a collector electrode; a collector on the collector electrode; a drift region on the collector; a plurality of first trench gates spaced apart from each other in the drift region; a floating first body region between first adjacent ones of the first trench gates and in the drift region, in a floating region of the insulated gate bipolar transistor; a second body region between second adjacent ones of the first trench gates and in the drift region, in an active region of the insulated gate bipolar transistor; a planar gate between the first adjacent ones of the first trench gates and on the first body region; and a second trench gate spaced apart from the first adjacent ones of the first trench gates in the first body region, and having a lowermost surface deeper than a lowermost surface of the first body region.
- Claim:
14. The insulated gate bipolar transistor of claim 13, wherein the second trench gate has a narrower width and a smaller vertical length than the first trench gates.
- Claim:
15. The insulated gate bipolar transistor of claim 14, wherein first body region has a lowermost surface at substantially a same depth as a lowermost surface of the first body region.
- Claim:
16. A method of manufacturing an insulated gate bipolar transistor, the method comprising: forming a drift region on a collector; forming a first body region in a drift region in a floating region of the insulated gate bipolar transistor; forming a plurality of first trench gates spaced apart from each other in the drift region; forming a planar gate on the first body region; forming a second body region in the drift region in an active region of the insulated gate bipolar transistor; forming an emitter in the second body region; forming an interlayer insulating layer on the first body region and the second body region and covering the planar gate; and forming an emitter electrode on the interlayer insulating layer.
- Claim:
17. The method of claim 16, wherein forming the plurality of first trench gates comprises: forming a plurality of first trenches having a first depth in the drift region; forming an insulating layer in the first trenches and on the first body region; and forming a polysilicon layer on the insulating layer to form the first trench gates.
- Claim:
18. The method of claim 17, further comprising forming a second trench having a second depth between a pair of the first trenches and in the first body region, forming the insulating layer in the second trench, and forming the polysilicon layer in the second trench, wherein the second depth is shallower than the first depth.
- Claim:
19. The method of claim 17, wherein forming the emitter electrode on the interlayer insulating layer comprises: forming a contact hole in the interlayer insulating layer in the active region; forming a body contact in the second body region through the contact hole; and forming a conductive layer in the contact hole and on the interlayer insulating layer.
- Claim:
20. The method of claim 17, wherein forming the planar gate comprises etching the polysilicon layer on the insulating layer.
- Current International Class:
01; 01; 01
- الرقم المعرف:
edspap.20240304708
Processing Request
No Comments.