- Document Number:
20230088494
- Appl. No:
18/070359
- Application Filed:
November 28, 2022
- نبذة مختصرة :
A method and system for culling a patch of surface data from one or more tiles in a tile based computer graphics system. A rendering space is divided into a plurality of tiles and a patch of surface data read. Then, at least a portion of the patch is analysed to determine data representing a bounding depth value evaluated over at least one tile. This may comprise tessellating the patch of surface data to derive a plurality of tessellated primitives and analysing at least some of the tessellated primitives. For each tile within which the patch is located, the data representing the bounding depth value is then used to determine whether the patch is hidden in the tile, and at least a portion of the patch is rendered, if the patch is determined not to be hidden in at least one tile.
- Claim:
1. A method in a tile based graphics system having a rendering space subdivided into a plurality of tiles, comprising: reading a patch of surface data; determining that the patch is present in a tile but not needed to render that tile, before rendering the tile; and rendering the tile without tessellating the patch.
- Claim:
2. The method according to claim 1, wherein said determination is performed on a non-per-pixel basis.
- Claim:
3. The method according to claim 1, wherein the determining step is performed before it is determined whether to tile the patch.
- Claim:
4. The method according to claim 1, wherein the determining step is performed after the patch is tiled.
- Claim:
5. The method according to claim 4, wherein the method comprises: storing an indication of the patch in a display list for the tile in which the patch is determined to be present; reading the display list for the tile; and determining that the patch indicated in the read display list is not needed to render the tile.
- Claim:
6. The method according to claim 1, wherein the determining step comprises: performing a first depth comparison test to determine whether the patch is needed to render the tile, before it is determined whether to tile the patch; only if it is not determined from the first depth comparison test that the patch is not needed to render the tile, tiling the patch and performing a second depth comparison test after tiling but before rendering the tile.
- Claim:
7. The method according to claim 1, the method further comprising determining the maximum and/or minimum depth value for the patch; and wherein the depth value for the patch is used to determine the patch is not needed to render the tile.
- Claim:
8. The method according to claim 7, wherein the determining step comprises comparing the depth value for the patch with a depth threshold for that tile to determine the patch is not needed to render the tile.
- Claim:
9. The method according to claim 1, wherein it is determined the patch is present in more than one tile, the method further comprising: determining a maximum and/or minimum depth value for the patch; for each tile in which the patch is present: comparing the depth value with a depth threshold for that tile to determine whether the patch is needed to render that tile, prior to rendering that tile; and rendering that tile without using the patch if it is determined that the patch is not needed to render that tile.
- Claim:
10. The method according to claim 1, the method further comprising: determining the minimum and/or maximum depth of the patch; and comparing the depth value of the patch with a depth threshold for that tile; wherein the method comprises determining that the patch is present in the tile but not needed to render the tile from the comparison of the depth value with the depth threshold.
- Claim:
11. The method according to claim 1, wherein the method further comprises culling the patch that is not needed to render the tile.
- Claim:
12. A graphics system for having a rendering space subdivided into a plurality of tiles, the system comprising: tessellation logic configured to read a patch of surface data; processing logic configured to determine that the patch is present in the tile but not needed to render the tile, prior to the tile being rendered; rendering logic configured to render the tile without tessellating the patch.
- Claim:
13. The graphics system according to claim 12, wherein the processing logic is configured to determine that the patch is present in the tile but not needed to render the tile, prior to the tile being rendered before it is determined whether to tile the patch.
- Claim:
14. The graphics system according to claim 12, wherein the processing logic is configured to determine that the patch is present in the tile but not needed to render the tile before hidden surface removal is performed on the tile and prior to the tile being rendered.
- Claim:
15. The graphics system according to claim 12, further comprising hidden surface removal logic configured to perform hidden surface removal on the tile, wherein the processing logic is configured to determine that the patch is present in the tile but not needed to render the tile, after the patch is tiled but before hidden surface removal is performed on the tile.
- Claim:
16. The graphics system according to claim 12, wherein the processing logic is configured to: perform a first depth comparison test to determine whether the patch is needed to render the tile, before it is determined whether to tile the patch; perform a second depth comparison test after tiling but before hidden surface removal is performed on the tile, only if it is not determined from the first depth comparison test that the patch is not needed to render the tile.
- Claim:
17. The graphics system according to claim 12, further comprising tiling logic configured to store an indication of the patch in a display list for the tile in which the patch is determined to be present; the processing logic being configured to read the display list for the tile, and determine that the patch indicated in the read display list is not needed to render the tile.
- Claim:
18. The graphics system according to claim 12, wherein the processing logic is configured to determine that the patch is present in the tile but not needed to render the tile.
- Claim:
19. The graphics system according to claim 18, further comprising depth-calculating logic configured to determine the minimum and/or maximum depth of the patch; wherein the processing logic is configured to compare the depth value of the patch with a depth threshold for that tile and determine that the patch is present in the tile but not needed to render the tile from the comparison of the depth value with the depth threshold.
- Claim:
20. A non-transitory computer-readable medium having stored thereon computer-readable program code defining an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a graphics system having a rendering space subdivided into a plurality of tiles, the graphics system comprising: tessellating logic configured to read a patch of surface data; processing logic configured to determine that the patch is present in the tile but not needed to render the tile, prior to the tile being rendered; and rendering logic configured to render the tile without tessellating the patch.
- Current International Class:
06; 06; 06; 06; 06
- الرقم المعرف:
edspap.20230088494
Processing Request
No Comments.