Array Substrate and Method of Fabricating the Same

20170229517

14/904489

December 25, 2015

The present invention proposes an array substrate and a method for fabricating the same. According to the array substrate and the method of fabricating the array substrate in the present invention, the IGZO pattern and the first electrode strip, the first channel, and the second metallic layer in the corresponding section form the first transistor of the CMOS inverter, and the OSC pattern and the second electrode strip, the second channel, and the second metallic layer in the corresponding section form the second transistor of the CMOS inverter. In this way, the CMOS inverter or the CMOS ring oscillator is fabricated based on IGZO and OSC.

Shenzhen China Star Optoelectronics Technology Co. Ltd. (Shenzhen, Guangdong, CN)

1. A method of fabricating an array substrate, comprising: forming a first metallic layer, a plurality common electrodes arranged along a predetermined direction, and an insulting layer on a substrate in order where the first metallic layer comprises a first electrode strip and a second electrode strip arranged at intervals along a predetermined direction, arranging each of the common electrodes between the first electrode strip and the second electrode strip which is adjacent to the first electrode strip, and forming a capacitor between the common electrode and the second metallic layer and the insulating layer in the corresponding section; forming an indium gallium zinc oxide (IGZO) pattern arranged at intervals on the insulating layer along the predetermined direction, and arranging the IGZO pattern above the first electrode strip; forming a second metallic layer on the insulating layer and the IGZO pattern layer, alternately arranging a first channel and a second channel on the second metallic layer along the predetermined direction, exposing a corresponding section of the first channel where the IGZO pattern is formed, exposing a corresponding section of the second channel where the insulating layer is formed, and locating the insulating layer above the second electrode strip; forming an organic semiconductor (OSC) pattern on the corresponding section of the second channel; forming a flat passivation layer on the insulating layer, the second metallic layer, the IGZO pattern, and the OSC pattern; wherein the first electrode strip, the first channel, and the second metallic layer and the IGZO pattern in a corresponding section form the first transistor, the second electrode strip, the second channel, and the second metallic layer and the OSC pattern in a corresponding section form the second transistor, and the first transistor and the second transistor are connected in series to form a complementary metal oxide semiconductor (CMOS) inverter, and wherein the first electrode strip and the second electrode strip both are gates of a thin film transistor (TFT) in the array substrate, the second metallic layer comprises a source and a drain of the TFT, the first channel and the second channel are alternately arranged between the source and the drain which is adjacent to the source along the predetermined direction, and the same drain is arranged between the first channel and the second channel which is adjacent to the first channel.

2. The method of claim 1, wherein the first electrode strip, the first channel, and the source, the drain, and the IGZO pattern in the corresponding section form the first transistor, the second electrode strip, the second channel, and the source, the drain, and the OSC pattern form the second transistor, the array substrate forms the plurality of CMOS inverters in an odd number, and a first CMOS inverter is connected to a a last CMOS inverter.

3. The method of claim 2, wherein the first transistor is an N-channel MOS transistor, and the second transistor is a P-channel MOS transistor.

4. A method of fabricating an array substrate, comprising: forming a first metallic layer and an insulting layer on a substrate in order where the first metallic layer comprises a first electrode strip and a second electrode strip arranged at intervals along a predetermined direction; forming an indium gallium zinc oxide (IGZO) pattern arranged at intervals on the insulating layer along the predetermined direction, and arranging the IGZO pattern above the first electrode strip; forming a second metallic layer on the insulating layer and the IGZO pattern layer, alternately arranging a first channel and a second channel on the second metallic layer along the predetermined direction, exposing a corresponding section of the first channel where the IGZO pattern is formed, exposing a corresponding section of the second channel where the insulating layer is formed, and locating the insulating layer above the second electrode strip; forming an organic semiconductor (OSC) pattern on the corresponding section of the second channel; forming a flat passivation layer on the insulating layer, the second metallic layer, the IGZO pattern, and the OSC pattern; wherein the first electrode strip, the first channel, and the second metallic layer and the IGZO pattern in a corresponding section form the first transistor, the second electrode strip, the second channel, and the second metallic layer and the OSC pattern in a corresponding section form the second transistor, and the first transistor and the second transistor are connected in series to form a complementary metal oxide semiconductor (CMOS) inverter.

5. The method of claim 4, wherein the first electrode strip and the second electrode strip both are gates of a thin film transistor (TFT) in the array substrate, the second metallic layer comprises a source and a drain of the TFT, the first channel and the second channel are alternately arranged between the source and the drain which is adjacent to the source along the predetermined direction, and the same drain is arranged between the first channel and the second channel which is adjacent to the first channel.

6. The method of claim 5, wherein the first electrode strip, the first channel, and the source, the drain, and the IGZO pattern in the corresponding section form the first transistor, the second electrode strip, the second channel, and the source, the drain, and the OSC pattern form the second transistor,the array substrate forms the plurality of CMOS inverters in an odd number, and a first CMOS inverter is connected to a a last CMOS inverter.

7. The method of claim 6, wherein the first transistor is an N-channel MOS transistor, and the second transistor is a P-channel MOS transistor.

8. The method of claim 4, wherein after the first metallic layer is formed on the substrate, the method further comprises: forming a plurality of common electrodes arranged alternatively on the substrate along the predetermined direction, arranging each of the common electrodes between the first electrode strip and the second electrode strip which is adjacent to the first electrode strip, and forming a capacitor between the common electrode and the second metallic layer and the insulating layer in the corresponding section.

9. An array substrate, comprising: a substrate; a first metallic layer and an insulting layer, formed on the substrate where the first metallic layer comprises a first electrode strip and a second electrode strip arranged at intervals along a predetermined direction; an indium gallium zinc oxide (IGZO) pattern above the first electrode strip, arranged at intervals on the insulating layer along the predetermined direction; a second metallic layer, formed on the insulating layer and the IGZO pattern layer, alternately arranging a first channel and a second channel on the second metallic layer along the predetermined direction, wherein a corresponding section of the first channel is uncovered by the IGZO pattern, a corresponding section of the second channel above the second electrode strip is uncovered by the insulating layer; an organic semiconductor (OSC) pattern, formed on the corresponding section of the second channel; a flat passivation layer, formed on the insulating layer, the second metallic layer, the IGZO pattern, and the OSC pattern; wherein the first electrode strip, the first channel, and the second metallic layer and the IGZO pattern in a corresponding section form the first transistor, the second electrode strip, the second channel, and the second metallic layer and the OSC pattern in a corresponding section form the second transistor, and the first transistor and the second transistor are connected in series to form a complementary metal oxide semiconductor (CMOS) inverter.

10. The array substrate of claim 9, wherein the first electrode strip and the second electrode strip both are gates of a thin film transistor (TFT) in the array substrate, the second metallic layer comprises a source and a drain of the TFT, the first channel and the second channel are alternately arranged between the source and the drain which is adjacent to the source along the predetermined direction, and the same drain is arranged between the first channel and the second channel which is adjacent to the first channel.

11. The array substrate of claim 10, wherein the first electrode strip, the first channel, and the source, the drain, and the IGZO pattern in the corresponding section form the first transistor, the second electrode strip, the second channel, and the source, the drain, and the OSC pattern form the second transistor, the array substrate forms the plurality of CMOS inverters in an odd number, and a first CMOS inverter is connected to a last CMOS inverter.

12. The array substrate of claim 11, wherein the first transistor is an N-channel MOS transistor, and the second transistor is a P-channel MOS transistor.

13. The array substrate of claim 9 further comprising: a plurality of common electrode, arranged alternatively on the substrate along the predetermined direction, wherein each common electrode is between the first electrode strip and the second electrode strip which is adjacent to the first electrode strip, and a capacitor is formed between the common electrode and the second metallic layer and the insulating layer in the corresponding section.

01

edspap.20170229517