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Foreground Static Error Calibration for Current Sources Using Backgate Body Biasing

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  • معلومة اضافية
    • Contributors:
      STMicroelectronics Grenoble (ST-GRENOBLE); Laboratoire Traitement et Communication de l'Information (LTCI); Institut Mines-Télécom Paris (IMT)-Télécom Paris; Microélectronique Silicium - IEMN (MICROELEC SI - IEMN); Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN); Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA); Université catholique de Lille (UCL)-Université catholique de Lille (UCL)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA); Université catholique de Lille (UCL)-Université catholique de Lille (UCL); STMicroelectronics; Institut Polytechnique de Paris (IP Paris); Département Communications & Electronique (COMELEC); Télécom ParisTech; Circuits et Systèmes de Communication (C2S); Institut Mines-Télécom Paris (IMT)-Télécom Paris-Institut Mines-Télécom Paris (IMT)-Télécom Paris; This work was supported in part by the Nano 2022 - IPCEI program.; Laboratoire commun STMicroelectronics-IEMN T2
    • بيانات النشر:
      HAL CCSD
    • الموضوع:
      2022
    • الموضوع:
    • نبذة مختصرة :
      International audience ; This work presents a detection and calibration circuit for current sources static mismatch introduced by the process of fabrication. The current is corrected through backgate body bias voltage control, which has the benefit of reduced additional parasitic elements, compared to more classic amplitude calibration or sort-and-map solutions. The main application are high speed and high resolution current steering Digital to Analog Converters (DAC). The calibration circuit is applied on a 2 timeinterleaved (TI) DAC, with 12 bits of resolution and sampled at a frequency of 16 GHz. Its main requirement is to be able to generate signals up to the Nyquist Band (8 GHz) with Spurious Free Dynamic Range (SFDR) of at least 70 dBFS. We validate the method with a schematic 28 nm FDSOI CMOS transistor level testbench, Montecarlo simulations and temperature variations from 27 °C to 125 °C.
    • Relation:
      hal-03760060; https://hal.science/hal-03760060; https://hal.science/hal-03760060/document; https://hal.science/hal-03760060/file/Beauquier%20RTSI%20published.pdf
    • الدخول الالكتروني :
      https://hal.science/hal-03760060
      https://hal.science/hal-03760060/document
      https://hal.science/hal-03760060/file/Beauquier%20RTSI%20published.pdf
    • Rights:
      info:eu-repo/semantics/OpenAccess
    • الرقم المعرف:
      edsbas.ED818DAC