Item request has been placed! ×
Item request cannot be made. ×
loading  Processing Request

Synthesis of Data-Flow Interfaces for Regular Parallel Programs

Item request has been placed! ×
Item request cannot be made. ×
loading   Processing Request
اقرأ أكثر حفظ في قائمتي
  • معلومة اضافية
    • Contributors:
      Codesign of Silicon Systems (COSI); Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA); Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes); Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes); Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-INRIA Rennes; Institut National de Recherche en Informatique et en Automatique (Inria); INRIA
    • بيانات النشر:
      HAL CCSD
    • الموضوع:
      1999
    • Collection:
      École Centrale Paris: HAL-ECP
    • نبذة مختصرة :
      We present a method for generating an interface between an architecture executing a regular program and a host processor, during an hardware-software co-design process. The interface is generated by static analysis of a single assignment Alfa program and of its scheduling. This method is implement- ed in the MMAlpha design environment, and was experimented on a H261 image coder.
    • Relation:
      Report N°: RR-3760; inria-00072902; https://inria.hal.science/inria-00072902; https://inria.hal.science/inria-00072902/document; https://inria.hal.science/inria-00072902/file/RR-3760.pdf
    • Rights:
      info:eu-repo/semantics/OpenAccess
    • الرقم المعرف:
      edsbas.E285071B