Fabrication of NMOS Logic Gates

NMOS logic gates were a predecessor to the CMOS logic gates widely used today. They allow for easier process steps and take into account the limited equipment that is available in the ODU clean room. In this thesis, NMOS logic gates were studied in order to open a new field of research into logic gates at Old Dominion University. This work focuses mostly on the designs of the mask patterns and the design of the fabrication process. NOT, NOR, NAND, OR, and AND gates were fabricated with transistors with a 75 µm gate length, using masks and processes specifically developed for our equipment, such as the maskless mask aligner. All gates fabricated demonstrated the expected behavior but with some limitations. Due to a high value on the on resistance for the transistor (Ron), the voltage divider between the on and off state of the transistor is not as distinguishable as in our simulations. This leads to a voltage range for the LOW or HIGH outputs to be narrower than anticipated, at 0 to 3 V and 3 to 4 V respectively. Future designs of the NMOS logic gates should work towards reducing the Ron value.