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Compact modeling and circuit design based on spin injection ; Modélisation compacte et conception de circuit à base d'injection de spin

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  • معلومة اضافية
    • Contributors:
      Institut des Nanotechnologies de Lyon (INL); École Centrale de Lyon (ECL); Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL); Université de Lyon-École Supérieure de Chimie Physique Électronique de Lyon (CPE)-Institut National des Sciences Appliquées de Lyon (INSA Lyon); Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS); Centre de Nanosciences et de Nanotechnologies Orsay (C2N); Université Paris-Sud - Paris 11 (UP11)-Université Paris-Saclay-Centre National de la Recherche Scientifique (CNRS); Université Paris Saclay (COmUE); Jacques-Olivier Klein
    • بيانات النشر:
      HAL CCSD
    • الموضوع:
      2017
    • Collection:
      HAL Lyon 1 (University Claude Bernard Lyon 1)
    • نبذة مختصرة :
      The CMOS technology has tremendously affected the development of the semi-conductor industry. However, as the technology node is scaled down, the CMOS technology faces significant challenges set by the leakage power and the short channel effects. To cope with this problem, researchers pay their attention to the spintronics in recent years, considering its possibilities to allow smaller size fabrication and lower power operations. The magnetic tunnel junction (MTJ) is one of the most important spintronic devices which can store binary data based on Tunnel MagnetoResistance (TMR) effect. Except for the non-volatile memory, MTJ can be also used to combine with or replace the CMOS circuits to implement a hybrid circuit, for the potential to achieve low power consumption and high speed performance. However, the problem of frequent spin-charge conversion in a hybrid circuit may cause large power consumption, which diminishes the advantage of the hybrid circuits. Therefore, the ASL concept which uses a pure spin current to transport the information is proposed for fewer charge-spin conversions, thus for less power consumption. The design of ASL device-based circuits leads to numerous challenges related to the heterogeneity they introduce and the large design space to explore. Hence, this thesis focus on filling the gap between application requirements at the system level and the device fabrication at the device level. In device level, we developed a compact model integrating the STT, the TMR, the spin injection/accumulation effects, the channel breakdown current and the spin diffusion delay. Validated by comparing with experimental results, this model allows exploring fabrication-related device parameters such as channel lengths and MTJ sizes and help designers to prevent from device damages. Moreover, programmed with Verilog-A on Cadence and divided into several blocks: injector, detector, channel and contact devices, this model allows the independent design and cross-layer optimization of ASL-based circuits, that ...
    • Relation:
      NNT: 2017SACLS240
    • الدخول الالكتروني :
      https://theses.hal.science/tel-01720258
      https://theses.hal.science/tel-01720258v1/document
      https://theses.hal.science/tel-01720258v1/file/72810_AN_2017_archivage.pdf
    • Rights:
      info:eu-repo/semantics/OpenAccess
    • الرقم المعرف:
      edsbas.3618A1D1