A Fault-Resistant Architecture for AES S-box Architecture.

This paper introduces a high-speed fault-resistant hardware implementation for the S-box of AES cryptographic algorithm, called HFS-box. A deep pipelining for S-box at the gate level is proposed. In addition, a new Dual Modular Redundancy-based (DMR-based) countermeasure is exploited in HFS-box for fault correction. The newly introduced countermeasure is a fault correction scheme based on the DMR technique (FC-DMR) combined with a version of the time redundancy technique. In the proposed architecture, when a transient random or malicious fault(s) is detected in each pipeline stage, the error signal corresponding to that stage increases. The control unit holds the previous correct value in the output of the proposed DMR voter in the other pipeline stages as soon as it observes the value '1' on the error signal. The previous correct outputs will be kept until the fault effect disappears. The presented low-cost HFS-box provides a high capability of fault resistance against transient faults with any duration by imposing low area overhead compared with similar fault correction strategies, i.e., 137%, and low throughput degradation, i.e., 11.3%, on the original S-box implementation. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Applied Research in Electrical Engineering is the property of Shahid Chamran University of Ahvaz and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)