EZ-FET : an electrical characterization test vehicle for process optimization of low temperature SOI substrates and devices ; EZ-FET : un dispositif de caractérisation électrique pour l'optimisation de procédés de fabrication à basse température de substrats et composants SOI

In the recent years, SOI (Silicon-On-Insulator) substrates and devices have seen numerous developments, exploring a wide range of technologies, materials and processes for various applications, such as the 3D sequential integration. To keep pace with these rapid advancements, a fast and reliable electrical characterization test-vehicle is mandatory to develop the technological bricks. Traditional test architectures are the pseudo-MOSFET (metal-oxide-semiconductor field effect transistor), widely used for SOI substrates and the entirely fabricated fully-depleted SOI FDSOI transistor for both substrate and device characterization. Even though largely employed, both have limitations: the pseudo-MOSFET cannot be adapted for the front-gate while the FDSOI MOSFET fabrication is long and costly.This thesis introduces the EZ-FET (easy MOSFET), a simple and innovative device that bridges the gap between the two classical characterization architectures. The EZ-FET is an FDSOI-like transistor, with only two lithography levels needed to define the active region and the front gate stack. It combines the fast, simple and cost-effective fabrication of the pseudo-MOSFET with the double-gated configuration of the FDSOI transistor.Subsequent to optimizing the EZ-FET device and customizing the characterization techniques and methodologies to fit its unique configuration, we focus on its use for low-temperature (LT) processes. One of the main challenges at LT (below 500°C) is the formation of the source/drain (S/D) junctions. Two approaches were evaluated to outcome this challenge. The first option involves the use of an EZ-FET with undoped S/D, removing completely the need of any activation, but bringing up a modelling issue, resolved by the development of an adapted electrical model and parameters extraction methodology. The second approach consists of the activation of S/D dopants by laser annealing, rather than standard furnace, giving raise this time to processing challenges that will be handled and validated through ...