Mobility Enhancement in Monolayer MoS 2 Transistors on a Polyimide Substrate by Reducing Localized Charge Trap Effect

Monolayer molybdenum disulfide (MoS 2 ) is a promising candidate for flexible electronics, but its electron mobility on polymer substrates is typically constrained to below 10 cm 2 V –1 s –1 . To investigate this limitation, we fabricate top-gated monolayer MoS 2 field-effect transistor (FET) on a polyimide substrate with a SiO x seed (SiO x FET). Our electron transport model reveals that the localized charge trapping (LCT) effect is the primary mobility-limiting mechanism. The sources of LCT, structural defects in the monolayer MoS 2 and interfacial defects from the SiO x seed layer, are systematically suppressed via a transfer optimization (TO) process and a vacuum annealing (VA) strategy, respectively. By combining TO with an optimized-VA strategy, the SiO x FET (TO+VA) achieves a high mobility of 24.8 cm 2 V –1 s –1 , demonstrating a significant mobility enhancement at low and high electron densities, compared to the untreated SiO x FET. Crucially, the dominant mobility-limiting mechanism shifts from the LCT effect in the untreated SiO x FET to Coulomb impurity scattering in the SiO x FET (TO+VA). The fundamental study underscores a model-guided approach to systematically mitigate the LCT effect, enabling high-mobility monolayer MoS 2 devices on polymer substrates.