MICROELECTRONIC DEVICES INCLUDING CONTACT STRUCTURES, AND RELATED MEMORY DEVICES, AND ELECTRONIC SYSTEMS

20240304722

18/424704

January 26, 2024

A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a staircase structure comprising steps comprising horizontal edges of the tiers, each of the steps comprising multiple tiers, and conductive contact structures vertically extending from a vertically upper surface of the stack structure to the conductive structures of the steps, the conductive structures defining each of the steps individually in contact with a conductive contact structure. Related memory devices and electronic systems are also described.

1. A microelectronic device, comprising: a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers; a staircase structure comprising steps comprising horizontal edges of the tiers, each of the steps comprising multiple tiers; and conductive contact structures vertically extending from a vertically upper surface of the stack structure to the conductive structures of the steps, the conductive structures defining each of the steps individually in contact with a conductive contact structure.

2. The microelectronic device of claim 1, wherein the each of the steps comprises three of the tiers.

3. The microelectronic device of claim 1, wherein the conductive structures contacting different conductive structures of the same step are electrically isolated from one another.

4. The microelectronic device of claim 1, wherein each of the conductive structures defining each of the steps is individually in electrical communication with two of the conductive contact structures.

5. The microelectronic device of claim 1, wherein a vertically uppermost surface of each of the steps comprises a surface of a vertically uppermost one of the insulative structures defining the step.

6. The microelectronic device of claim 1, wherein the conductive contact structures individually exhibit a greater dimension in a first horizontal direction than in a second horizontal direction.

7. The microelectronic device of claim 1, wherein, for each of the steps, the conductive contact structures vertically extend to the conductive structures outside of horizontal boundaries of a vertically uppermost level insulative structure defining the step.

8. The microelectronic device of claim 1, wherein conductive contact structures in contact with conductive levels defining one of the steps are located within horizontal boundaries of one another in a horizontal direction in which the steps of the staircase structure vertically ascend and descend.

9. The microelectronic device of claim 1, further comprising pillar structures each at least partially within horizontal boundaries defining one of the steps and at least partially outside of the horizontal boundaries defining the one of the steps, the pillar structures individually vertically extending through the stack structure.

10. A memory device, comprising: a stack structure comprising tiers each comprising a conductive structure and an insulative structure vertically neighboring the conductive structure; staircase structures comprising steps comprising horizontal edges of the tiers, the steps individually defined by more than one of the tiers; a first conductive contact structure in contact with a vertically uppermost conductive structure of one of the steps; a second conductive contact structure in contact with a vertically uppermost conductive structure of the one of the steps, the second conductive structure farther from a horizontal center of the one of the steps in a first horizontal direction than the first conductive contact structure; and strings of memory cells vertically extending through portions of the stack structure neighboring the staircase structures in a second horizontal direction.

11. The memory device of claim 10, further comprising pillar structures vertically extending through the stack structure at the horizontal edges of the tiers.

12. The memory device of claim 11, wherein a first portion of each of the pillar structures is located outside of horizontal boundaries of the steps in the second horizontal direction and a second portion of the pillar structures are located within horizontal boundaries of the steps in the second horizontal direction.

13. The memory device of claim 10, further comprising a slot structure horizontally extending through the memory device in second first horizontal direction and separating the memory device into block structures each individually comprising some of the staircase structures.

14. The memory device of claim 13, wherein the first conductive contact structure is located closer to the slot structure than the second conductive contact structures.

15. The memory device of claim 10, wherein the first conductive contact structure and the second conductive contact structure individually comprise a contact connection region vertically between the one of the steps and a vertically uppermost surface of the stack structure.

16. The memory device of claim 15, wherein the first conductive contact structure and the second conductive contact structure individually horizontally extend in the first horizontal direction within the contact connection region.

17. An electronic system, comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising at least one microelectronic device, the at least one microelectronic device comprising: a stack structure comprising a vertically alternating sequence of levels of insulative structures and levels of conductive structures arranged in tiers; staircase structures having steps comprising horizontal edges of the tiers, each of the steps defined by horizontal edges of at least two of the tiers; conductive contact structures individually vertically extending from a vertically uppermost surface of the stack structure and contacting each of the levels of the conductive structure of each of the steps; and strings of memory cells horizontally neighboring the staircase structures and vertically extending through the stack structure.

18. The electronic system of claim 17, wherein the each of the steps are defined by horizontal edges of three of the tiers.

19. The electronic system of claim 17, wherein conductive contact structures in contact with portions of vertically uppermost conductive structures defining the steps are located farther from a center of the staircase structure than the conductive contact structures in contact with vertically lowermost conductive structures defining the steps.

20. The electronic system of claim 17, wherein each conductive level of each step is individually in contact with two of the conductive contact structures.

01; 10; 10

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